It is generally desirable to construct electrical circuits capable of high speed operation. In an electrical circuit containing MOSFETs, this requires the MOSFETs themselves to have rapid response to input signals. A significant barrier to achieving higher operating speeds of MOSFETs has been overcoming the parasitic gate capacitance of the MOSFET, where a significant amount of delay is incurred while charging and discharging the gate of the MOSFET to a certain voltage in order to amplify a signal or to fully switch the MOSFET on and off.
FIG. 1a shows a representative vertical MOSFET with the gate-source parasitic capacitance (C.sub.GS) and the gate-drain parasitic capacitance (C.sub.GD) shown. Also shown in FIG. 1a is the drain-source parasitic capacitance (C.sub.DS).
To operate the N channel MOSFET of FIG. 1a, a positive voltage V.sub.DD is applied to drain terminal 20, while a low voltage (e.g., ground) is applied to source regions 30 and body regions 34. Source regions 30 and body regions 34, which constitute the emitter and base of a parasitic NPN bipolar transistor, are imperfectly shorted together by contacts 36 to prevent these regions from being forward biased. Conductive gate 38 is insulated from source regions 30 and body regions 34 by a gate oxide. When a gate-source voltage V.sub.GS is applied to gate 38 which exceeds the threshold voltage V.sub.T of the MOSFET, an ohmic channel forms in body regions 34 undergate 38 so as to ohmically couple N-type source regions 30 to N-type drain 40. Current is then conducted between source contacts 36 and drain terminal 20. When the MOSFET is in its off state, a depletion region, represented by dashed outline 44, is created within drain 40.
A basic equivalent circuit for the MOSFET of FIG. 1a is shown in FIG. 1b. As shown in FIG. 1b, for the gate 50 to have a voltage V.sub.G necessary to fully turn on MOSFET 52, both C.sub.GS and C.sub.GD must be fully charged. Capacitance C.sub.DS will be considered herein to approximate zero. Also shown in FIG. 1b is input gate current IG and current I.sub.C.sbsb.GD charging capacitor C.sub.GD. Note that source region 30, body region 34, and drain 40 form a parasitic NPN bipolar transistor within the MOSFET, as shown in FIG. 1b.
A vertical MOSFET, such as shown in FIG. 1a, is typically a polysilicon gate device, where the gate 38 is used as a diffusion mask to self-align source regions 30 and body regions 34.
FIG. 2 illustrates the voltage conditions during a dynamic switching operation for a representative MOSFET C.sub.GD with a constant current I.sub.G applied at t=0. In region 1 of the graph of FIG. 2, the MOSFET is off, with V.sub.GS below the threshold voltage V.sub.T. Input gate current I.sub.G is shared between C.sub.GD and C.sub.GS according to their capacitance ratio Within region 2, the threshold voltage V.sub.T is reached and the MOSFET begins to turn on, lowering the drain-to-source voltage V.sub.DS. This changing VDS sets up a condition where the voltage is changing more rapidly across C.sub.GD than C.sub.GS. Current increases in C.sub.GD and decreases in C.sub.GS, thus reducing the rate at which V.sub.GS is increasing. As V.sub.GS becomes larger, the dv/dt of the drain-to-source voltage V.sub.DS increases until the current I.sub.C.sbsb.GD charging C.sub.GD reaches a magnitude equal to I.sub.G, and V.sub.GS no longer increases. This condition results in the flat portion of the V.sub.GS curve in region 3 of FIG. 2.
During this time, the depletion region under the gate, generally shown as depletion region 44 in FIG. 1a, decreases since the potential of drain 40 under gate 38 is lowered due to this region being pulled down by the increasing ohmic channel between N-type source region 30 and N-type drain 40. During the entire turn-on period of the MOSFET, capacitance C.sub.GD is increasing due to this narrowing of the effective insulation between the plates of the equivalent capacitor C.sub.GD. As this capacitance increases, a decreasing dv/dt of the drain-to-source voltage V.sub.DS results. This increase in capacitance C.sub.GD is reflected in the curved lower portion of V.sub.DS shown in FIG. 2.
Once capacitance C.sub.GD has stabilized, the MOSFET is essentially fully on, and C.sub.GD does not cause any further switching delay.
As seen by the gate charge characteristics of FIG. 2, the delay in switching of the MOSFET is significantly affected by capacitance C.sub.GD, where capacitance C.sub.GD is more commonly referred to as the reverse transfer capacitance (C.sub.rss). Since, as shown in FIG. 2, capacitance C.sub.GD is affected by voltage changes at the drain, it becomes understandable how the effective total gate capacitance (C.sub.in) of the MOSFET under dynamic conditions is calculated using the following equation: EQU C.sub.in =C.sub.GS +C.sub.GD (1-A.sub.V), (eq. 1)
where A.sub.V =dV.sub.DS /dV.sub.GS.
For an N channel MOSFET, dV.sub.DS will be a negative value, and for a P channel MOSFET, dV.sub.GS will be a negative value. Thus, in either case, (1-A.sub.V) is equal to (1+voltage gain).
It is also to be noted that essentially the same gate charge characteristics are encountered with the discharging of the gate, which causes the turn-off speed of the MOSFET to be delayed. In linear applications, such as radio frequency (RF) power amplification, input capacitance largely determines the upper frequency limit of the MOSFET.
Typically, the value C.sub.GD (1-A.sub.V) is at least three times greater than C.sub.GS, and thus any reduction of capacitance C.sub.GD will significantly lower the switching time of the MOSFET, or significantly raise the usable operating frequency.
Capacitance is calculated using the equation: EQU C=AK.epsilon..sub.O /t, (eq. 2)
where
C is the capacitance; PA1 .epsilon..sub.O is the permitivity of empty space (8.85.times.10.sup.-2 coul.sup.2 /newton.sup.2 -m.sup.2); PA1 K is the dielectric constant (3.9 for SiO.sub.2 and 11.7 for Si); PA1 A is the plate area; and PA1 t is the dielectric thickness.
Thus, capacitance may be reduced by decreasing the plate area or increasing the dielectric thickness.
The prior art has attempted to reduce the parasitic gate capacitance of a MOSFET by reducing the area of the gate and/or increasing the effective dielectric thickness between the gate and the drain.
Two types of approaches which have been previously used to reduce C.sub.GD are shown in FIGS. 3 and 4 where, in FIG. 3, an increased thickness of dielectric 60 is formed over drain 62 to provide an increased dielectric thickness between gate 64 and drain 62. The gate-source capacitance C.sub.GS is essentially unchanged, since the thickness of the dielectric separating gate 64 from source region 66 is essentially unchanged.
Prior art FIG. 4 illustrates an approach where an N channel vertical MOSFET uses two separate gates 70 and 72 commonly connected to a gate voltage V.sub.G. Since the effective area of the gate over drain 76 is decreased, the C.sub.GD is also decreased.
One drawback of the MOSFET of prior art FIG. 3 is that gate 64 may be misaligned with respect to raised dielectric portion 60, causing part of the device to have low gain. In FIG. 4, a center portion of the gate oxide 70 over drain 76 must be masked and protected while body regions 78 and source regions 74 are formed self-aligned with the gate. Also in FIG. 4, the width of gate elements 72 is subject to mask and photoresist variations, which cause variations in C.sub.GD across a wafer and from lot to lot. The critical masking steps required to form raised dielectric portion 60 in FIG. 3 and to perform the precise etching of the gate in FIG. 4 require a relatively precise alignment of the mask, or relatively precise process and mask control, thus inevitably resulting in lower yields and variable performance devices.
Another drawback to the MOSFET in FIG. 3 is the imperfect short across the emitter-base of the parasitic bipolar transistor. Under certain adverse conditions, the bipolar transistor may be turned on to the extent of causing secondary breakdown and device failure. Manufacturers have addressed this problem by: 1) reducing the depth of the N+source diffusion to lower beta; 2) moving the P+body contact region closer to the channel region to reduce resistance between the emitter and base; and 3) reducing the lateral dimension of the N+ source region to lower the resistance between the emitter and base.
What is needed in the art is a MOSFET structure having a relatively low C.sub.GD and an inoperative parasitic bipolar transistor which may be formed with self-aligned source, body, and body contact regions and which may be formed without requiring numerous and difficult process steps.